Many wireless communication standards use block codes, such as turbo codes, to increase the performance of channel decoding. In block coding techniques, the encoding and decoding processes are done on a block-by-block basis. Many standards, such as WiBro, CDMA2000 and WCDMA, use turbo encoding and decoding functions that handle different block sizes, spanning from a few bits to 20 kilobits (e.g., CDMA2000).
Processing an entire block at one time requires sufficient memory to hold all of the intermediate results. By way of example, a dedicated alpha memory is used to hold alpha values that are calculated during a forward processing of the trellis in a turbo decoder. These intermediate result memories may consume at least half of the total turbo decoder memory, including the input-output (I/O) buffers. These intermediate result memories increase proportionally with the block size.
Conventional block decoders reduce these memory requirements by introducing block segmentation techniques, in which the received data block is divided into smaller segments and the smaller segments are then processed one at a time. This reduces the intermediate result memory requirements according to the selected segment size. Unfortunately, switching the intermediate results in and out of memory between segments introduces a large amount of processing overhead, which decreases the supported bit rate significantly.
Therefore, there is a need in the art for an improved reconfigurable decoder for use in a software-defined radio (SDR) system. In particular, there is a need for a maximum a posteriori probability (MAP) decoder that uses a reduced amount of memory to perform channel decoding.